1. Customer Challenge
In the spring of 2018, a defense prime contractor awarded a contract to develop the transmit/receive module (TRM) for the naval overlay of a next-generation Active Electronically Scanned Array (AESA) radar. The program had aggressive size, weight, power, and cost (SWaP-C) targets and a 10-year service life requirement in a marine environment — meaning salt spray, thermal cycling, and high humidity.
The TRM housing had to fit within a envelope of 40 mm × 25 mm × 6 mm. The thermal challenge was severe: the GaN HEMT power amplifier dies would dissipate 8–10 W of heat, and the baseplate — mounted to an aluminum liquid-cooled cold plate — was specified at a maximum of 85°C. Junction temperature for the GaN dice was not to exceed 150°C.
The program required MIL-STD-883 Class B screening — the most rigorous screening class specified for hybrid microcircuits in military space and high-reliability applications. Class B demands an extensive flow of tests including thermal cycling, constant acceleration, particle impact noise detection (PIND), internal water vapor content (WVI) test, burn-in, and both fine and gross leak testing. First article delivery was required within 18 months of contract award.
With 10-year reliability targets and zero tolerance for field failures on a naval weapons system, the prime needed an assembly partner who was ITAR-registered, had a demonstrated track record with GaN-on-LTCC assemblies, and could deliver production quantities at acceptable cost.
2. Solution: LTCC + Thick Film Hybrid
The selected architecture was a 12-layer LTCC (Low-Temperature Co-fired Ceramic) substrate using a glass-ceramic composition with relative permittivity εr = 5.9. LTCC was chosen for its ability to integrate passive components — resistors, capacitors, and inductors — within the substrate layers, reducing the module's footprint while improving RF performance by minimizing parasitic interconnect lengths.
The RF architecture on the LTCC surfaces used thick film gold (TF-Au) conductors, screen-printed and fired at approximately 850°C. The TF-Au process provided 15–20 μm thick conductors with good conductivity (sheet resistance < 3 mΩ/sq) and excellent wire bondability. Via interconnects between LTCC layers were filled with silver-bearing pastes and co-fired with the substrate.
The power amplifier stage used GaN HEMT dice from Qorvo (model family TGF2023-02 or equivalent) — a 28V GaN-on-SiC device specified for X-band operation. Driver amplifiers and limiting functions were implemented in GaAs MMICs from two domestic suppliers. The integrated 90° hybrid couplers — required for the quadrature feed network — were implemented as stripline structures within the LTCC layers, eliminating the need for a discrete hybrid component.
The bias-T network (combining DC bias with the RF signal path) was also embedded in the LTCC, using a combination of multilayer ceramic capacitors for RF bypassing and spiral inductors in the substrate. This level of integration was only possible because of LTCC's ability to embed passives across multiple layers.
Manufacturing was performed at a US-based, ITAR-registered hybrid assembly facility with experience in GaN assembly and LTCC processing. The facility had a Class 1000 (ISO 6) cleanroom for die attach and wire bonding operations, a resistance seam welder with closed-loop current control, and a He leak detection system calibrated to MIL-STD-883 Method 1014.
3. Specifications Achieved
The production-representative modules met or exceeded all electrical specifications over the full 8–12 GHz operating band. Measured results from the Lot 1 qualification build (77 pieces) are summarized below.
| Parameter | Specification | Measured (typ.) | Notes |
|---|---|---|---|
| Frequency Range | 8–12 GHz | 7.9–12.1 GHz | 1 dB bandwidth exceeds requirement |
| Noise Figure | ≤ 2.5 dB @ 10 GHz | 2.1 dB @ 10 GHz | GaN LNA stage contribution |
| Output Power | ≥ 40 W CW | 42 W CW | At 28V drain, 10 GHz |
| Power-Added Efficiency (PAE) | ≥ 30% | 35% | Exceeded at midband |
| Phase Noise | ≤ –105 dBc/Hz @ 10 kHz | –108 dBc/Hz @ 10 kHz | Integrated LO chain contribution |
| Gain Flatness | ±1.0 dB across band | ±0.8 dB | Across 8–12 GHz |
| Input VSWR | ≤ 1.5:1 | 1.3:1 | DC–12 GHz |
| Output VSWR | ≤ 1.5:1 | 1.3:1 | DC–12 GHz |
| Thermal Resistance (Rth jc) | ≤ 2.5°C/W | 2.1°C/W | Junction-to-case, GaN PA stage |
The output power and PAE performance were particularly notable. GaN-on-SiC delivers superior power density compared to GaAs — approximately 5–10 W/mm versus 1–2 W/mm for GaAs — enabling the required 40 W CW output in the 40 mm × 25 mm footprint. The PAE of 35% at 10 GHz, while modest by GaN standards, was acceptable for the naval radar application where average power — not peak efficiency — drove thermal design.
4. Thermal Management Approach
Thermal management was the most technically challenging aspect of the program. With 8–10 W of dissipated heat in a 40 mm × 25 mm module, the thermal density exceeded 10 W/cm² — comparable to some CPU applications.
The primary heat removal path was through the bottom of the module. An AlN spreader plate (thermal conductivity 170 W/m·K) was eutectically attached to the back of the LTCC substrate using AuSn die attach. The AlN spreader distributed the heat flux from the GaN dice (concentrated under each transistor cell) across the full baseplate area before it entered the liquid-cooled cold plate.
Within the LTCC substrate, a thermal via array was implemented directly beneath each GaN die location. These vias were filled with a Cu-Invar-Mo composite stack — Cu for thermal conductivity, Invar for CTE compensation, and Mo as a stress-isolation layer. This material stack was chosen over pure copper-filled vias because the Invar layer reduced the effective CTE of the via stack, limiting stress on the LTCC during thermal cycling.
At the baseplate interface, 3M Tgon 920 thermal interface material (TIM) was used — a thermal gap filler with rated conductivity of 7 W/m·K, applied at 30 mils thickness. Tgon 920 was selected over thermal greases for its compliance (it conformed to surface irregularities without pumping out) and its long-term stability in temperature cycling environments.
Die attach for the GaN dice used 80Au/20Sn eutectic gold-tin solder, applied by precision dispensing and reflowed in a forming gas atmosphere. AuSn was chosen over silver-glass die attach because it provided the highest thermal conductivity at the die-attach interface (~80 W/m·K for a void-free bondline) and excellent long-term reliability at the GaN operating temperatures. Kirkendall voiding was a concern (see Section 7), but was controlled through process specification.
Thermal simulation was performed in ANSYS Icepak, correlated against IR thermography measurements on first-article hardware. The simulation-to-measurement correlation was within 8°C at the GaN junction under worst-case conditions. This early correlation — performed on prototype hardware before production release — proved to be one of the most valuable program decisions (see Lessons Learned).
5. MIL-STD-883 Screening Results
The complete MIL-STD-883 Class B screening flow is specified in MIL-STD-883, Notice 12 (or later revisions as specified). The sequence below reflects the order implemented for this program, which follows the Method 5004 template for hybrid microcircuits.
Screening Flow
- Visual inspection (Method 2010, internal)
- Temperature cycling (Method 1010, Condition C: –65°C to +150°C, 20 cycles)
- Constant acceleration (Method 2001, 5,000g, Y1 direction)
- PIND (Method 2020, Particle Impact Noise Detection)
- Internal water vapor content (Method 1018, Gross Leak: ≤5,000 ppm H₂O)
- Pre-cap inspection (Method 2010, external)
- Seal — Fine leak (Method 1014, Condition B, R₁ ≤ 5 × 10⁻⁸ atm·cm³/s) + Gross leak (Method 1014, Condition A)
- Burn-in (Method 1035, 160 hours at +125°C, bias applied)
- Final electrical (Room temperature, 100% RF parameters)
- Post burn-in electrical (Room temperature, full RF parameters)
- External visual (Method 2009)
Screening Results — Lot 1 (n = 77)
| Screening Step | Result | Defects Found |
|---|---|---|
| C-SAM (pre-screening sample) | 0 delamination | None |
| Temperature cycling (20 cycles) | 100% pass | 0 |
| Constant acceleration (5000g) | 100% pass | 0 |
| PIND | 98.7% pass (76/77) | 1 loose particle detected; failed unit rejected |
| Internal water vapor | 100% pass | All < 3,500 ppm |
| Fine leak (He mass spec) | 100% pass | All R₁ < 1 × 10⁻⁸ atm·cm³/s |
| Gross leak (bubble) | 100% pass | 0 |
| Burn-in (160 hr @ +125°C) | 94% first-pass yield | 4 units failed; 1 infant mortality identified (gate oxide defect), 3 wear-out related |
| Final electrical (post burn-in) | 100% pass (72 surviving) | 0 |
| Overall yield (built to shipped) | 93.5% (72/77) | 5 failures across all steps |
The 94% first-pass burn-in yield was considered excellent for a Class B GaN hybrid at this power level. The four burn-in failures were submitted for FA (failure analysis). Three showed wear-out signatures consistent with long-term gate stress; one was an infant mortality attributable to a gate oxide defect in a GaAs driver IC — not the GaN PA stage. The infant mortality rate of 1.3% (1/77) was within the expected population rate for this IC technology.
6. Five-Year Reliability Data
The program entered production in late 2018 and ran through 2023, delivering 12 production lots averaging 72 modules each (864 total modules delivered over 5 years). A reliability monitor program tracked field performance, HTOL data, and returns.
High Temperature Operating Life (HTOL)
HTOL testing was performed quarterly on 22-module samples from each production lot, at an ambient of 150°C (above the 125°C Class B limit) with nominal bias. Test duration: 1,000 hours per quarterly sample. The activation energy for the GaN wear-out mechanism was determined to be approximately 0.7 eV from Arrhenius extrapolation, consistent with published GaN reliability literature.
Environmental and Characterization Testing
| Test | Condition | Sample Size | Failures | Result |
|---|---|---|---|---|
| HTOL | 150°C, 1008 hr, bias | 22/lot × 5 lots | 2 | PASS — both infant mortality, same root cause (gate oxide defect in GaAs IC, corrective action implemented) |
| Temperature-Humidity-Bias (THB) | 85°C / 85% RH, 1,000 hr | 15 | 0 | PASS — hermetic seal maintained; no corrosion failures |
| High Temperature Storage | 175°C, 1,000 hr | 10 | 0 | PASS — no mechanical degradation observed |
| Thermal Shock | –65°C to +150°C, 500 cycles | 10 | 0 | PASS — no delamination on C-SAM post-stress |
| TID (Total Ionizing Dose) | 100 krad(Si), Co-60 source | 6 | 0 | PASS — GaN shown to be relatively TID-tolerant vs. GaAs; both passed Class S requirement |
Field Performance at 5 Years
Of 864 modules delivered across 5 years of production, zero field failures attributable to the hybrid module were reported by the prime contractor's field support team. The MTBF calculation, using the chi-squared method on the demonstrated failure-free field data plus the HTOL test hours, yielded:
- Demonstrated MTBF: 87,000 hours at 70°C (90% lower confidence bound)
- Worst-case FIT rate: ~13 FIT (failures in 10⁹ device-hours)
The failure mechanism distribution (FMD) for the program was: 60% random infant mortality (caught in burn-in and early field operation, predominantly the GaAs driver IC defect mode) and 40% wear-out (GaN PA gain compression at end-of-life, caught in HTOL monitoring). No seal-related failures were observed in the field, validating the MIL-STD-883 leak testing approach.
7. Lessons Learned
Three engineering lessons from this program had outsized impact on the final outcome.
Early Thermal Simulation Saved Months
The decision to perform IR thermography correlation on prototype hardware in Month 3 of the program — well before production release — identified a 15°C discrepancy between the initial thermal model and measured results. The root cause was an under-specified thermal via fill in the LTCC substrate. Correcting the via design (increasing fill factor from 60% to 80%, switching from Ag to Cu-Invar-Mo) required a substrate respin. Had this been discovered during qualification rather than during prototype debug, the respin would have caused a 3-month schedule delay.
Kirkendall Voiding in AuSn Die Attach
Early HTOL samples showed 3 of 22 modules with degraded thermal resistance after 500 hours at 150°C. Cross-sectional analysis revealed Kirkendall voiding at the AuSn/Ni/Ta interface — a ~8% void fraction in the die attach layer, concentrated at the die corners. The root cause was insufficient Ni barrier thickness (only 50 μin specified) combined with a 260°C die attach reflow profile that exceeded the Au-Ni interdiffusion activation threshold.
The corrective action: Ni barrier thickness was increased to 100 μin minimum, and the reflow profile was changed to a lower peak temperature (310°C peak, 30-second dwell above liquidus). A void fraction specification of <5% by C-SAM was added to the process control plan. After the change, zero voiding was observed in subsequent lots.
LTCC Via Resistance Variation
During first-pass electrical test of Lot 2, 4 of 77 modules showed elevated resistance on DC bias lines routed through LTCC buried vias. Investigation revealed that the Ag-bearing via fill paste lot-to-lot variation was causing sheet resistance variation of ±15% on the buried DC bus layers. The corrective action was 100% incoming resistance test of LTCC substrates before assembly, with acceptance criteria of ±10% from nominal. Process control charts were also established for the via fill process parameters (paste viscosity, squeegee pressure, via fill speed).
8. Conclusion
The X-band TRM program demonstrated that GaN-on-LTCC is a viable and reliable technology platform for defense RF modules requiring high power density, integrated passives, and MIL-STD-883 Class B screening. The 93.5% overall yield from a complex 12-layer LTCC GaN hybrid exceeded program expectations.
The key engineering decisions that drove success were: the use of LTCC for embedded passives (reducing module size and improving RF performance), early thermal simulation with hardware correlation (avoiding a 3-month schedule slip), the AuSn die attach process with void fraction control (preventing premature thermal resistance degradation), and the comprehensive MIL-STD-883 Class B screening flow (achieving zero field failures across 864 modules over 5 years).
The program is applicable to similar programs: any X-band or Ku-band TRM for AESA radar, electronic warfare, or satellite communications that requires high output power in a small footprint with long-term reliability in a harsh environment.